1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and a method for manufacturing the same, and more specifically relates to an insulated gate semiconductor device which realizes on-resistance reduction in an up-drain structure having a drain electrode provided on the same principal surface as a source electrode, and a method for manufacturing the same.
2. Description of the Related Art
There has been known an insulated gate semiconductor device having a so-called up-drain structure which enables surface mounting by drawing a drain region onto a principal surface of a substrate where a source electrode is formed. This technology is described for instance in Japanese Patent Application Publication No. 2000-200902.
With reference to a cross-sectional view of FIG. 10, description will be given of a conventional insulated gate semiconductor device having a so-called up-drain structure which enables surface mounting, by taking a MOSFET as an example.
On a p type silicon semiconductor substrate 110, n− type semiconductor layers 111 and 112 are provided. Moreover, a p+ type impurity region 113 is provided to extend to the n− type semiconductor layer 111 from the n− type semiconductor layer 112. A p type impurity region (p type well region W′) is provided in a surface of the n− type semiconductor layer 112 and an element region E′ of a MOSFET is provided in a surface of the p type well region W′.
In the element region E′, trenches 115 are provided in an n− type channel layer 121, inner walls of the trenches 115 are covered with gate insulating films 116, and gate electrodes 117 are embedded in the trenches 115. In the surface of the p type impurity region W′ adjacent to the trench 115, a p+ type source region 114 is provided. Each of the trenches 115 is covered with an interlayer insulating film 118, and a source electrode 120 is provided so as to be connected to the source region 114 in each cell.
On the n− type semiconductor layer 112, a drain electrode 126 is provided. The drain electrode 126 comes into contact with a high concentration p type impurity region 119 provided in the n− type semiconductor layer 112. The p type impurity region 119 comes into contact with the p+ type impurity region 113 buried in the n− type semiconductor layers 111 and 112 and forming a part of a drain region, and serves as a conductive path for drawing a drain current up to a surface of the substrate.
As described above, the MOSFET having the up-drain structure includes the p+ type impurity region (buried region) 113, the p type impurity region 119 serving as the conductive path for drawing up the drain current, and the low concentration p type impurity region (p type well region W′). Moreover, the element region E′ of the MOSFET is formed in the p type well region W′.
However, an impurity concentration of the p type well region W′ that is a diffusion region is lower toward its bottom portion. This leads to a problem of increased resistance. In the MOSFET having the up-drain structure, a current path is formed to extend in the buried region 113 and the p type impurity region 119 below the element region E′. However, since the impurity concentration is low at the bottom of the p type well region W′, a resistance value of the current path in a direction perpendicular to the substrate is increased below the element region E′. This leads to a problem of increased on-resistance.
Moreover, since an impurity concentration of the buried region 113 is higher than that of the p type well region W′, a degree of upward diffusion (so-called swelling) is sometimes increased by heat treatment in formation of the buried region 113.
Specifically, the buried region 113 extends to the p type well region W′ layer by the swelling. Therefore, a desired depth for the p type well region W′ layer can no longer be secured. This leads to a problem of breakdown voltage deterioration.
Moreover, the bottom portion of the p type well region W′ is positioned at a depth of about 4.5 μm from its surface, for example. Therefore, there is a problem that ion implantation into this region to compensate for the lowered impurity concentration is difficult to perform even by use of high acceleration energy.